Parallella Reference Manual 4.12.2.13 typos v2556.2.16 by mrgs

page #1 :

(1)  ZYNQ7010 should be ZYNQ7020
(2)  Band widths at Epiphany FPGA, North, South 1.4GB/s should be [1.4|1.6]GB/s, (vs page #7)
(3)  Band width between FPGA and GPIO : 2.5GB/s should be 2.85GB/s (vs page #7)
(4)  FLASH should be [QSPI|BOOT] NOR FLASH
(5)  Missing 'JTAG' connection

page #3 :

(6)  Epiphany-IV Datasheet link e16g401 should be e64g401  

page #4 :

(7)  (4)

page #6 :

(8)  'a16-core' should be 'a 16-core'
(9)  Zynq7000 Series should be Zynq7020 
(10) 64-cire should be 64-core
(11) Missing I2C, UART, SPDIF @  Expansion Connectors (PWR)

page #7 :

(12) a missing ')'

page #8 :

(13) Figure 1 (Parallella Connectivity Diagram) : missing I2C, UART, SPDIF, 'GP' LEDs, RESET BTN  

page #9 : 

(14) Figure 2 (Zynq Connectivity Diagram) : missing QSPI FLASH
 
page #11:

(15) (4)

Questions: 

- SDIO at SD?
- Zynq boot source selection? (What about the device mode pins?) 
- 3-pin 'Berg' connector for what? : RESET / UART / BOOT CONFIG / MEASUREMENT / ...
- Figure 2 : 800 MHz (XC7Z020-3CLG400C) (!) FIXME : '-3' plus 'C', speed grade and temperature range.
- SDIO_1 : MIO[15:10]? Figure 1. 
